List of Selected Publications by Research Topics 

 Data Converters  

1. 2016 (IEEE TCAS-I) An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS 

2. 2018 (IEEE JSSC) A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation 

3. 2020 (IEEE JSSC) A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer

 Cryogenic Quantum Computing Projects

1. 2023 (IKEEE) CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer

2. 2023 (IEEE ACCESS) Analysis of Quarter Method Applied ROM-based DDFS Architecture

3. 2024 (IEEE TCAS-II) A 4.3 GS/s Time-Interleaved ∆Σ DAC with temperature-insensitive bias and Harmonic cancellation for Qubit Control

4. 2024 (IKEEE) Measurement set-up for CMOS-based integrated circuits and systems at cryognic temperature

 PUF Integrated Circuits and Systems for Security Projects

1. 2022 (IEEE ACCESS) Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique

2. 2022 (Electronics) Stochastic Cell- and Bit-Discard Technique to Improve Randomness of a TRNG 

3. 2023 (IEEE TCAS-II) High-speed Light Detection Sensor for Hardware Security in Standard CMOS Technology

4. 2024 (Electronics) A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

5. 2024 (Sensors) A lightweight and high yield CMOS TRNG with lightweight Photon post-processing

6. 2024 (IEEE Transactions) Reconfigurable SRAM-based PUF (Submitted)

 AMS Design Automations Projects 

1. 2022 (Electronics) Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition

2. 2023 (IEEE ACCESS) AMS Circuit Design Optimization Technique Based on ANN Regression Model with VAE Structure (Editor's Selected paper)

 Big Data Sciences 

1. 2024 (Applied Sciences) Solving Optimal EV Chargers Deployment Problem

 List of All Journal Publications (After join SeoulTech)

[J24, 2024.10]  Chi Trung Ngo, Hyun Woo Ko, Ji Woo Choi, Jae-Won Nam, *Jong-Phil Hong,   A lightweight and high yield CMOS TRNG with lightweight Photon post-processing Sensors (vol. 24 (23), no. 7502, pp. 1-13), SCIE-Q2, IF:3.4 @ 2023 DOI: https://doi.org/10.3390/s24237502 Funding: IITP-2024-2020-0-01462, NRF-2021R1A2C2005258

[J23, 2024.10] Jae-Yun Park, *Jae-Won Nam,   A 4.3 GS/s Time-Interleaved ∆Σ DAC with temperature-insensitive bias and harmonic cancellation for Qubit Control IEEE Transactions on Circuits and Systems II: Express-Briefs (vol. 71, no. 11, pp. 4663-4667) ISICAS-2024 Special Issue, SCIE-Q2, IF: 4.0 DOI: https://doi.org/10.1109/TCSII.2024.3470111 Funding: NRF-2022R1A4A3029433, IITP-2023-RS-2022-00156295

           

[J22, 2024.06] Hyeonsik Ahn, Yoonseuk Choi, Junghwan Han, Jae-Won, Nam, Kunhee Cho, *Jusung Kim Measurement set-up for CMOS-based integrated circuit and systems at cryogenic temperature Journal of IKEEE (ISSN: 1226-7244), KCI DOI: https://doi.org/10.7471/ikeee.2024.28.2.174 Funding: NRF-2022R1A4A3029433

[J21, 2024.06] Seungmo Kim, Yeonho Jeong, *Jae-Won Nam, Solving Optimal EV Chargers Deployment Problem  Applied Sciences (vol. 14 (12), no. 5092, pp. 1-19), SCIE-Q1, IF: 2.5 DOI: https://doi.org/10.3390/app14125092 Funding: SeoulTech-U2021-0380

        

[J20, 2024.01] Van Khanh Pham, Chi Trung Ngo, Jae-Won Nam, *Jong-Phil Hong, A Reconfigurable SRAM CRP PUF with High Reliability and Randomness  Electronics (vol. 13 (2), no. 309, pp. 1-13), SCIE-Q2, IF:2.6 DOI: https://doi.org/10.3390/electronics13020309 Funding: NRF-2020R1A6A1A12047945, NRF-2021R1A2C2005258

[J19, 2023.10] Jaeyun Park, Suhyeon Kim, Hyunyoung Yoo, *Jae-Won Nam, Analysis of Quarter Method Applied ROM-based DDFS Architecture IEEE ACCESS (vol. 11, pp. 117137-117148), SCIE-Q2, IF:3.9  DOI: https://doi.org/10.1109/ACCESS.2023.3325938 Funding: NRF-2022R1A4A3029433, IITP-2023-RS-2022-00156295

[J18, 2023.05] Dana Kim, Jong-Phil Hong, Jiwon Lee, *Jae-Won Nam, High-speed Light Detection Sensor for Hardware Security in Standard CMOS Technology  IEEE Transactions on Circuits and Systems II: Express-Briefs (vol. 70, no. 10, pp. 3917-3921) ISICAS-2023 Special Issue, SCIE-Q2, IF: 4.4 DOI: https://doi.org/10.1109/TCSII.2023.3289407 Funding: NRF-2021R1A2C2005258, IITP-2023-RS-2022-00156295

[J17, 2023.05] Jinwon Hyun, *Jae-Won Nam, AMS Circuit Design Optimization Technique Based on ANN Regression Model with VAE Structure  IEEE ACCESS (vol. 11, pp. 58850-58862), SCIE-Q2, IF:3.9 DOI: https://doi.org/10.1109/ACCESS.2023.3285113 Funding: IITP-2023-RS-2022-00156295

[J16, 2023.01]  Jusung Kim, Junghwan Han, *Jae-Won, Nam, *Kunhee Cho, CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer DOI: https://doi.org/10.7471/ikeee.2023.27.1.12 Journal of IKEEE (ISSN: 1226-7244), KCI Funding: NRF-2022R1A4A3029433

[J15, 2022.05] Jae-Won Nam, Jaewoo Kim, Jong-Phil Hong,  Stochastic Cell- and Bit-Discard Technique to Improve Randomness of a TRNG Electronics (vol. 11, no. 11, pp. 1-16), SCIE-Q2, IF:2.9  DOI: https://doi.org/10.3390/electronics11111735 Funding: NRF-2021R1A2C2005258, IITP-2022-2020-0-01462

[J14, 2022.02] Jae-Won Nam, Jaewoo Kim, Jong-Phil Hong, Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique  IEEE ACCESS (vol. 10, pp. 22311-22319), SCIE-Q2, IF:3.9 DOI: https://doi.org/10.1109/ACCESS.2022.3153359 Funding: NRF-2021R1A2C2005258, NRF-2020R1A6A1A12047945

[J13, 2022.01] Jae-Won Nam, Young-Kyun Cho, Youn Kyu Lee,  Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition  Electronics (vol. 11, no. 3, pp. 1-15), SCIE-Q2, IF:2.9  DOI: https://doi.org/10.3390/electronics11030408 Funding: NRF-2021R1G1A1003326

[J12, 2021.10] Young-Kyun Cho, Jae-Won Nam, Sang-Won Lee, A Low-Power Class-C Voltage-Controlled Oscillator with Robust Start-Up and Compact High-Q Capacitor Array  IEEE Transactions on Circuits and Systems II: Express-Briefs (vol. 69, no. 03, pp. 819-823), SCIE-Q2, IF:3.692  DOI: https://doi.org/10.1109/TCSII.2021.3116978 Funding: NRF-2021R1F1A1056073

[J11, 2021.11] Young-Kyun Cho, Jae-Won Nam, Three-Dimensional Selective Oxidation Fin Channel MOSFET Based on Bulk Silicon Wafer  Journal of Convergence for Information Technology (vol. 11, no. 11, pp. 159-165), KCI DOI: http://doi.org/10.22156/CS4SMB.2021.11.11.159 Funding: SeoulTech

       

[J10, 2021.09] Jae-Won Nam, Young-Kyun Cho,  5-bit FLASH A/D Converter Employing Time-interpolation Technique  Journal of Convergence for Information Technology (vol. 11, no. 9, pp. 124-129), KCI  DOI: https://doi.org/10.22156/CS4SMB.2021.11.09.124 Funding: SeoulTech

 Submitted

[J26, 2024.##]

Kwangmin Yu, Jimin Yoo, Hyunyoung Yoo, Jae-Yun Park, Jong-Phil Hong, *Jae-Won Nam

(Tentative) Reconfigurable SRAM-based PUF 

IEEE Transactions ####

Funding: NRF-2021R1A2C2005258, IITP-2023-RS-2022-00156295 

[J25, 2024.##]

Hapsah Aulia Azzahra, Muhammad Fakhri Mauludin, Xi Zhu, Jae-Won Nam, *Jusung Kim

15.4-17 GHz, -187.4 dBc/Hz FoM VCO with Current Reused Coupled Oscillator and Improved Noise Circulation

IEEE Transactions on Circuits and Systems I, Reg. Papers (Under Review 2nd round)

Funding: NRF-2021R1I1A304418211, NRF-2022R1A4A3029433

• J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer,” IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 557 - 567, Mar. 2020.

• J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1765-1779, Jun. 2018

• J.-W. Nam, and S.-W. M. Chen, “An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 10, pp. 1628 - 1638, Oct. 2016.

• J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “A 12-Bit 200-MS/s pipelined A/D converter with sampling skew reduction technique,” Elsevier Microelectronics Journal, no. 11, vol. 42, pp. 1225-1230, Nov. 2011.

• Y.-D. Jeon, J.-W. Nam, K.-D. Kim, T. M. Roh, and J.-K. Kwon, “A dual-channel pipelined ADC with sub-ADC based on flash–SAR architecture,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 11, pp. 741–745, Nov. 2012.

• H. B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “Single-chip A/D converter for digital microphones with on-chip preamplifier and time-domain noise isolation,” Electronics Letter, vol. 45, no. 3, pp. 151-153, 2009.

• Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 9-bit 80 MS/s successive approximation register analog-to-digital Converter with a capacitor reduction technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, pp. 502–506, Jul. 2012.

• Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications,” Elsevier Microelectronics Journal, vol. 42, no. 12, pp. 1335–1342, Jul. 2011.

• Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, S. -C, Lee, and J.-K. Kwon, “A 1.2 V 12 b 60 MS/s CMOS analog front-end for image signal processing applications,” Elsevier ETRI Journal, vol. 31, no. 6, Dec. 2009.