| Type | Author | Title | Journal Name | Funding | IF | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
SCIE-Q1 (2024.04) |
Jae-Yun Park, *Jae-Won Nam |
(Tentative) A 4.3 GS/s Time-Interleaved ∆Σ DAC for Qubit Control |
IEEE Transactions # |
NRF-2022R1A4A3029433 IITP-2023-RS-2022-00156295 |
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SCIE-Q2 (2024.04) |
Kwangmin Yu, Jimin Yoo, Jae-Yun Park, Jong-Phil Hong, *Jae-Won Nam |
(Tentative) Reconfigurable SRAM-based PUF |
IEEE Transactions # |
NRF-2021R1A2C2005258 IITP-2023-RS-2022-00156295 |
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SCIE-Q2 (2024.04) |
Seungmo Kim, Yeonho Jeong, Youlim Choi, Sunghyun Im, Hansoo Jung, *Jae-Won Nam |
Optimizing EV Chargers Location via Integer Programming |
IEEE Open Journal of Intelligent Transportation Systems |
SeoulTech |
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SCIE-Q2 | Van Khanh Pham, Chi Trung Ngo, Jae-Won Nam, *Jong-Phil Hong | A Reconfigurable SRAM CRP PUF with High Reliability and Randomness | MDPI Electronics |
NRF-2020R1A6A1A12047945 NRF- 2021R1A2C2005258
| 2.9 | ||||||
| SCIE-Q2 (2023.10) | Jaeyun Park, Suhyeon Kim, Hyunyoung Yoo, *Jae-Won Nam | Analysis of Quarter Method Applied ROM-based DDFS Architecture | IEEE ACCESS (vol. 11, pp. 117137-117148) | NRF-2022R1A4A3029433 IITP-2023-RS-2022-00156295 | *3.9 | ||||||
SCIE-Q2 (2023.05) | Dana Kim, Jong-Phil Hong,Jiwon Lee, *Jae-Won Nam | High-speed Light Detection Sensor for Hardware Security in Standard CMOS Technology | IEEE Transactions on Circuits and Systems II: Express-Briefs (vol. 70, no. 10, pp. 3917-3921, ISICAS-2023) | NRF-2021R1A2C2005258 IITP-2023-RS-2022-00156295 | *4.4 | ||||||
| SCIE-Q2 (2023.05) |
Jinwon Hyun, *Jae-Won Nam |
AMS Circuit Design Optimization Technique Based on ANN Regression Model with VAE Structure | IEEE ACCESS (vol. 11, pp. 58850-58862) |
IITP-2023-RS-2022-00156295 |
*3.9 | ||||||
| KCI (2023.01) |
Jusung Kim, Junghwan Han, *Jae-Won, Nam, *Kunhee Cho |
CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer | Journal of IKEEE ISSN: 1226-7244 |
NRF-2022R1A4A3029433 | - | ||||||
| SCIE-Q2 (2022.05) |
Jae-Won Nam, Jaewoo Kim, Jong-Phil Hong |
Stochastic Cell- and Bit-Discard Technique to Improve Randomness of a TRNG | MDPI Electronics (vol. 11, no. 11, pp. 1-16) |
NRF-2021R1A2C2005258 IITP-2022-2020-0-01462 |
2.9 | ||||||
| SCIE-Q2 (2022.02) |
Jae-Won Nam, Ju-Hyeok Ahn, Jong-Phil Hong |
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique | IEEE ACCESS (vol. 10, pp. 22311-22319) |
NRF-2021R1A2C2005258 NRF-2020R1A6A1A12047945 |
3.9 | ||||||
| SCIE-Q2 (2022.01) |
Jae-Won Nam, Young-Kyun, Cho, Youn Kyu Lee |
Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition | MDPI Electronics (vol. 11, no. 3, pp. 1-15) |
NRF-2021R1G1A1003326 | 2.9 | ||||||
SCIE-Q2 (2021.10) |
Young-Kyun, Cho, Jae-Won Nam, Sang-Won Lee |
A Low-Power Class-C Voltage-Controlled Oscillator with Robust Start-Up and Compact High-Q Capacitor Array |
IEEE Transactions on Circuits and Systems II: Express-Briefs (vol. 69, no. 03, pp. 819-823) |
NRF-2021R1F1A1056073 |
3.692 | ||||||
KCI | Young-Kyun, Cho, Jae-Won Nam | Three-Dimensional Selective Oxidation Fin Channel MOSFET Based on Bulk Silicon Wafer | Journal of Convergence for Information Technology | SeoulTech | - | ||||||
| KCI (2021.09) | Jae-Won Nam, Young-Kyun, Cho | 5-bit FLASH A/D Converter Employing Time-interpolation Technique | Journal of Convergence for Information Technology (vol. 11, no. 9, pp. 124-129) | SeoulTech | - |
Previous PublicationsJ.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer,” IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 557 - 567, Mar. 2020.
J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1765-1779, Jun. 2018
J.-W. Nam, and S.-W. M. Chen, “An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 10, pp. 1628 - 1638, Oct. 2016.
J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “A 12-Bit 200-MS/s pipelined A/D converter with sampling skew reduction technique,” Elsevier Microelectronics Journal, no. 11, vol. 42, pp. 1225-1230, Nov. 2011.
Y.-D. Jeon, J.-W. Nam, K.-D. Kim, T. M. Roh, and J.-K. Kwon, “A dual-channel pipelined ADC with sub-ADC based on flash–SAR architecture,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 11, pp. 741–745, Nov. 2012.
H. B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “Single-chip A/D converter for digital microphones with on-chip preamplifier and time-domain noise isolation,” Electronics Letter, vol. 45, no. 3, pp. 151-153, 2009.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 9-bit 80 MS/s successive approximation register analog-to-digital Converter with a capacitor reduction technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, pp. 502–506, Jul. 2012.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications,” Elsevier Microelectronics Journal, vol. 42, no. 12, pp. 1335–1342, Jul. 2011.
Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, S. -C, Lee, and J.-K. Kwon, “A 1.2 V 12 b 60 MS/s CMOS analog front-end for image signal processing applications,” Elsevier ETRI Journal, vol. 31, no. 6, Dec. 2009.
