Analog Integrated Circuit Design Lab.


Jaewon Nam 



 Assistant Professor 

Seoul National University of Science and Technology (Seoultech)
Dept. of Electronic Engineering 


  jaewon.nam at seoultech.ac.kr      +82-2-970-6478      Changhak-Hall #233

  Google Scholar Citations 

  Curriculum Vitae


 Research interests 

  AMS integrated circuit design (Analog/RF/Digital), 

  Machine learning (Mixed-signal Accelerator), 

  Cryogenic CMOS,

  Hardware security


Education 


 Ph.D. in Electrical Engineering 

     University of Southern California, CA, USA, 2019 (Electro-Physics)
     Thesis: Energy-Efficient Design Technique and Architecture for High-speed (GS/s) Analog-to-Digital Converters

    Advisor: Mike Shuo-Wei Chen


 M.S. in Electrical Engineering 

     University of Southern California, CA, USA, 2018 (Electro-Physics) 


 M.S. in Electrical Communication Engineering 

     Korea Advanced Institute of Science and Technology (KAIST), 2008
     Thesis: Systematic power optimizing cyclic ADC design
     Advisor: Sang-Gug Lee 


 B.S. in Electrical Communication Engineering 

    Korea Advanced Institute of Science and Technology (KAIST), 2006
    Graduate with Honor 


 Kyungbuk Science High School, Mar. 2001 - Feb. 2003


 Work Experiences


 2020 - Present, SeoulTech / Assistant Professor

 2019 - 2020, Intel Corporation, OR, USA / Analog Engineer
 2017 - 2017, Intel Corporation, CA, USA / Graduate Intern 
 2012 - 2008, Electronics and Telecommunications Research Institute (ETRI), South Korea / Research Staff 
 2006 - 2007, Electronics and Telecommunications Research Institute (ETRI), South Korea / Graduate Intern
 2023. IEEE International SoC Design Conference (ISOCC) Technical Program Committee Member (Data Converters)

Honors and Awards 

 2020, SeoulTech Online-Lecture Contest Recognition 
 2019, IEEE CICC Best Student Paper Award 
 2012, USC Viterbi School of Engineering Ph.D. Fellowship 
 2009, President Award, ETRI 
 2006, President Award, KAIST 

Invited Talks

 2021.09. GS/s ADC Design Trends for the High-speed Links (Host: Dr. Jae-Duk Han, RF/Analog Workshop)
 2021.02. ADC-based wireline receiver design (Host: Dr. Jong-Phil Hong, CNBU)
 2020.12. ADC-based wireline receiver (Host: Seung-eun Lee, ISE)
 2020.10. 25Gbps High-speed PAM4 wireline transceiver (Host: Dr. Lee, Ja-Yol, ETRI) 
 2019.06. ADC-based wireline receiver (Host: Dr. O'mahony, Frank, Intel corporation) 
 2019.05. Low power ADC design technique (Host: Dr. Grace, Carl, Lawrence Berkeley National Laboratory) 
 2019.02. Advanced High-speed ADC (Host: Dr. Choi Seungkeun, Univ. of Washington Bothell) 
 2019.01. Advanced High-speed ADC (Host: Dr. Wang, Hua, Georgia Tech)
 2018.10. ADC-based wireline receiver (Host: Dr. Gambhir, Manisha, Marvell Semiconductor)
 2013.08. Embedded Passive gain SAR ADC (Host: Dr. Su, David, Qualcomm Atheros)