Publications

 International Conference Papers 


 2023
J.-Y. Park, S.-H. Kim, J.-W. Nam, "Analysis of ROM-based DDFS Architecture Employing Quarter Method", International Conference on Electronics, Information, and Communication (ICEIC) 2023, Singapore, Feb. 2023. 
J.-W. Hyun, J.-W. Nam, "Regression Model-based VCO Design Optimization Technique", International Conference on Electronics, Information, and Communication (ICEIC) 2023, Singapore, Feb. 2023.
D. Kim, J.-W. Nam, J.-P. Hong, "Analysis of Silicon Photodiodes", International Conference on Electronics, Information, and Communication (ICEIC) 2023, Singapore, Feb. 2023.
 2021 
S. Park, J.-W. Nam, and S. K. Gupta, “HW-BCP: A custom hardware accelerator for SAT suitable for single chip implementation for large benchmarks,” the 26th Asia and South Pacific Design Automation Conf., Jan. 2021. 
J.-W. Nam and Y. K.  Lee, "Machine-learning based analog and mixed-signal circuit design and optimization," the 35th International Conf. on Information and networking (ICOIN), Jan. 2021.
H. W. Kwon, J.-W. Nam, and Y. K. Lee, “Generative adversarial attacks on fingerprint recognition systems,” the 35th International Conf. on Information and networking (ICOIN), Jan. 2021.​

 Domestic Conference Papers
 2024

안현식o, 남재원*, 한정환**, 조건희***, 김주성 (한밭대학교,서울과학기술대학교*,충남대학교**,경북대학교***), "Measurement Set-up for Integrated Circuits and Systems at Cryogenic Temperature", KIEES-2024 동계학술대회

 박재윤, 남재원, "4GS/s 4-Way Time-Interleaved Noise-Shaped DAC for Qubit Control using Quarter Method DDFS", KIEES-2024 동계학술대회
 2023 
Y.-L. Choi, S.-H., Im, H.-S. Jung, S.-M. Kim, and J.-W. Nam, "Machine Learning based EV Charger Location Optimization", Summer Annual Conference of IEIE, Jeju, June. 2023. (Outstanding Student Paper Award) 
 2022
H.-J. Lee, H.-C. Lee, J. Yoo, Y.-K. Cho, *J.-W. Nam, "Analysis on Efficiency of DC-DC Converter through Power-Loss Modeling & Measurement", the 5th ISE Conf., Seoul, Dec. 2022. 
H. Yoo, J.-W. Hyun, J.-W. Nam, "인공신경망을 이용한 부트스트랩 S/H 설계 최적화", the 5th ISE Conf., Seoul, Dec. 2022.

J.-W. Hyun, J.-Y. Kim, S.-J. Kim, *J.-W. Nam, "Study on Jitter Analysis and Reduction Methods in DLL", Fall annual conference of IEIE, Gonjiam, Nov. 2022.

H.-C. Lee, H.-J. Lee, J. Yoo, J.-W. Nam, “Loss analysis and modeling of asynchronous buck-converter”, Summer annual conference of IEIE, Jeju, Jun. 2022.

D. Kim, H. Yoo, J.-W. Nam, “Implementation of low-cost linear CMOS temperature sensor for biomedical application”, Summer annual conference of IEIE, Jeju, Jun. 2022.

J. Yoo, J.-W. Nam, J.-P. Hong, “Study on discard-rate of SRAM-based PUF”, Summer Annual Conference of IEIE, Jeju, Jun. 2022.

 Previous Achievements
 
J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS,” IEEE Custom Integrated Circuits Conf., Apr, 2019. (Best Student Paper Award) 
J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “Low-power High Dynamic-range ADC with over GHz Bandwidth using Cost-efficient Multi-bit/cycle SAR ADC,” GOMATech 2018.

J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2016, pp.154–156. 

J.-W. Nam, D. Chiong, and S.-W. M. Chen, “A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65 nm CMOS,” IEEE Custom Integrated Circuits Conf., Sep. 2013, pp. 1–4.

J.-W. Nam, Y.-D. Jeon, S.-J. Yun, T. M. Roh, and J.-K. Kwon, “A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS,” in Proc. IEEE ISOCC, 2011, pp. 405–407. 

J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, S.-G. Lee, and J.-K. Kwon, “A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS,” in Proc. IEEE ESSCIRC, 2009, pp. 468–471.

 D. Kang, H. Lim, J.-W. Nam, M. S.-W. Chen, J. Yoon, “VCSEL-Based Stretchable Blood Flow Sensors”, A meeting of the materials Research Society, Boston, U.S., Nov. 2017.
 Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, W.-Y. Lee, K.-T. Hong, and J.-K. Kwon, “A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS,” IEEE Custom Integrated Circuits Conf., Sep. 2010, pp. 1–4.
 H.-B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “A CMOS sigma-delta modulator for a digital electret microphone with a high input-impedance preamplifier,” 15th Korean Conference on Semiconductors, Phyeong-Chang, Feb. 2008.